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| DATA SHEET MOS INTEGRATED CIRCUIT PD75336 4-BIT SINGLE-CHIP MICROCOMPUTER DESCRIPTION The PD75336 is one of the "75X-series" 4-bit single-chip microcomputers enabled to process data with performance equivalent to that of 8-bit microcomputers. The PD75336 is a microcomputer with an expanded capacity of the ROM and RAM of conventional PD75328 and an improved 8-bit data processing capacity. It can carry out A/D converter low-voltage operations. For evaluation purposes for system development or small-quantity production, the PD75P336 is available which is a product with the on-chip mask ROM of PD75336 replaced with a one-time PROM. Functions are described in detail in the following User's Manual, which should be read when carrying out design work. PD75336 User's Manual: IEU-725 FEATURES * PD75328 upward compatible * Instruction execution time variable function useful for high-speed operations and power saving * 0.95, 1.91, 3.81, 15.3 s (Main system clock: When operated at 4.19 MHz) * 122 s (Subsystem clock: When operated at 32.768 kHz) * Memory capacity: PD75336 ROM: 16256 x 8 bits RAM: 768 x 4 bits * On-chip 8-bit resolution A/D converter (successive approximation type): 8 channels * Low-voltage operation possible: VDD = 2.7 to 6.0 V * On-chip LCD controller/driver * Maximum of 20 x 4 segments drive possible * Improved timer functions: 4 channels * Improved 8-bit data processing capability * Transfer, add/subtract, increase/decrease and compare possible * Ultra-compact package in use (80-pin plastic TQFP (fine pitch)( 12 mm)) * On-chip PROM (PD75P336) operative at low voltages available * VDD = 2.7 to 6.0 V APPLICATIONS Cameras, VCR integrated cameras, air conditioners, sphygmomanometers, etc. The information in this document is subject to change without notice. The mark 5 shows major revised points. Document No. IC-2893C (O.D. No. IC-7972C) Date Published February 1994 P Printed in Japan (c) NEC Corporation 1991 PD75336 ORDERING INFORMATION Ordering Code Package 80-pin plastic QFP ( 14 mm) 80-pin plastic TQFP (fine pitch)( 12 mm) PD75336GC-xxx-3B9 PD75336GK-xxx-BE9 Remarks "xxx" is a ROM code number. QUALITY GRADE Ordering Code Package 80-pin plastic QFP ( 14 mm) 80-pin plastic TQFP (fine pitch)( 12 mm) Quality Grade Standard Standard PD75336GC-xxx-3B9 PD75336GK-xxx-BE9 Remarks "xxx" is a ROM code number. Please refer to "Quality Grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 2 PD75336 GENERAL DESCRIPTION OF FUNCTIONS Item Instruction execution time ROM RAM General register Function When main system clock is selected: 0.95, 1.91, 3.81, 15.3 s (when operated at 4.19 MHz) When subsystem clock is selected: 122 s (when operated at 32.768 kHz) 16256 x 8 bits 768 x 4 bits * 4-bit manipulation: 8 x 4 banks * 8-bit manipulation: 4 x 4 banks 8 pins I/O line (The dual function pins for LCD-drive are included. The dedicated pins for LCD-drive are excluded.) 20 pins 44 8 pins 8 pins CMOS input pins CMOS input/output pin CMOS output pin N-ch open-drain input/output Use of pull-up resistor enabled by software (except P00) Dual function with segment pins 10 V withstand voltage. On-chip specification of pull-up resistor enabled by mask option On-chip memory LCD controller/driver * Output pins for LCD-drive * Segment output pins: 20 pins (dual-function pins with CMOS output: 8 pins) * Common output pins: 4 pins * Maximum 20 x 4 segment drive * Display mode selection: Static 1/2, 1/3, 1/4 duties On-chip 8-bit resolution A/D converter (successive approximation type) * 8-channel analog input * Low-voltage operable VDD = 2.7 to 6.0 V * A/D conversion speed 40.1 s (when operated at 4.19 MHz) * 8-bit timer/event counter x 2 channels * 8-bit basic interval timer * Watch timer ... 0.5 sec time interval generation, buzzer output possible (2 kHz, 4 kHz, 32 kHz) A/D converter Timer 4 channels Serial interface Bit sequential buffer Clock output (PCL) Buzzer output (BUZ) Vectored interrupt * NEC standard serial bus interface (SBI) * Clocked serial interface Special bit manipulation memory: 16 bits , 524 kHz, 262 kHz, 65.5 kHz (when operated at 4.19 MHz) 2 kHz, 4 kHz, 32 kHz (with main system clock or subsystem clock in operation) * External: 3 * Internal: 4 * External: 1 * Internal: 1 Transfer, add/subtract, increase/decrease and compare * Ceramic/crystal oscillator for main system clock oscillation : 4.194304 MHz * Crystal oscillator for subsystem clock oscillation : 32.768 kHz STOP/HALT mode VDD = 2.7 to 6.0 V * 80-pin plastic QFP ( 14 mm) * 80-pin plastic TQFP (fine pitch)( 12 mm) Test input 8-bit data processing System clock oscillator Standby Operating voltage Package 3 PD75336 CONTENTS 1. 2. 3. PIN CONFIGURATION (TOP VIEW) ......................................................................................................... 5 BLOCK DIAGRAM ...................................................................................................................................... 7 PIN FUNCTIONS ........................................................................................................................................ 8 3.1 3.2 3.3 3.4 3.5 PORT PINS .......................................................................................................................................................... 8 NON-PORT PINS ............................................................................................................................................... 10 PIN INPUT/OUTPUT CIRCUITS ...................................................................................................................... 12 MASK OPTION SELECTION ............................................................................................................................ 15 RECOMMENDED CONNECTION OF UNUSED PINS .................................................................................... 15 4. 5. MEMORY CONFIGURATION .................................................................................................................. 16 PERIPHERAL HARDWARE FUNCTIONS ................................................................................................ 19 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 PORTS ................................................................................................................................................................ 19 CLOCK GENERATOR ........................................................................................................................................ 20 CLOCK OUTPUT CIRCUIT ................................................................................................................................ 21 BASIC INTERVAL TIMER ................................................................................................................................. 22 WATCH TIMER .................................................................................................................................................. 23 TIMER/EVENT COUNTER ................................................................................................................................ 24 SERIAL INTERFACE .......................................................................................................................................... 26 LCD CONTROLLER/DRIVER ............................................................................................................................ 28 A/D CONVERTER ............................................................................................................................................. 30 5.10 BIT SEQUENTIAL BUFFER .............................................................................................................................. 31 6. 7. 8. 9. INTERRUPT FUNCTIONS ........................................................................................................................ 32 STANDBY FUNCTIONS ........................................................................................................................... 34 RESET FUNCTIONS ................................................................................................................................. 35 INSTRUCTION SET .................................................................................................................................. 38 10. ELECTRICAL SPECIFICATIONS .............................................................................................................. 46 11. PACKAGE INFORMATION ...................................................................................................................... 60 12. RECOMMENDED SOLDERING CONDITIONS ....................................................................................... 62 APPENDIX A. DIFFERENCES BETWEEN PD75336 AND PD75328 FUNCTIONS ................................ 63 APPENDIX B. DEVELOPMENT TOOLS ....................................................................................................... 64 APPENDIX C. RELATED DOCUMENTS ...................................................................................................... 65 4 PD75336 1. PIN CONFIGURATION (TOP VIEW) * 80-pin plastic QFP ( 14 mm) * 80-pin plastic TQFP (fine pitch)( 12 mm) P73/KR7 P72/KR6 P71/KR5 P70/KR4 P63/KR3 P62/KR2 P61/KR1 P60/KR0 RESET X2 X1 IC* XT2 XT1 VDD AVREF AVSS AN5 AN4 S31/BP7 S30/BP6 S29/BP5 S28/BP4 S27/BP3 S26/BP2 S25/BP1 S24/BP0 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 1 2 3 4 5 6 7 8 9 8079787776 757473 7271 70696867666564636261 AN3 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 AN2 AN1 AN0 P83/AN7 P82/AN6 P81 P80/TI1 P33 P32 P31/SYNC P30/LCDCL P23/BUZ P22/PCL P21/PTO1 P20/PTO0 P13/TI0 P12/INT2 P11/INT1 P10/INT0 P03/SI/SB1 PD75336GC-xxx-3B9 PD75336GK-xxx-BE9 10 11 12 13 14 15 16 17 18 19 20 2122232425 262728 2930 31323334353637383940 * Internally connected. Connect the IC PIN to VDD directly. P50 P51 P52 P53 P00/INT4 P01/SCK P02/SO/SB0 COM0 COM1 COM2 COM3 BIAS VLC0 VLC1 VLC2 P40 P41 P42 P43 VSS 5 PD75336 PIN NAMES P00 to P03 P10 to P13 P20 to P23 P30 to P33 P40 to P43 P50 to P53 P60 to P63 P70 to P73 P80 to P83 BP0 to BP7 KR0 to KR7 AVREF AVSS AN0 to AN7 SCK SI SO : : : : : : : : : : : : : : : : : Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Bit Port 0 to 7 Key Return 0 to 7 Analog Reference Analog Ground Analog Input 0 to 7 Serial Clock Serial Input Serial Output SB0,1 : RESET : S12 to S31 : COM0 to COM3 : VLC0 to VLC2 : BIAS : LCDCL : SYNC : TI0, 1 : PTO0, 1 : BUZ : PCL : INT0, 1, 4 : INT2 : X1, 2 : XT1, 2 : IC : VDD : VSS : Serial Bus 0, 1 Reset Segment Output 12 to 31 Common Output 0 to 3 LCD Power Supply 0 to 2 LCD Power Supply Bias Control LCD Clock LCD Synchronization Timer Input 0, 1 Programmable Timer Output 0, 1 Buzzer Clock Programmable Clock External Vectored Interrupt 0, 1, 4 External Test Input 2 Main System Clock Oscillation 1, 2 Subsystem Clock Oscillation 1, 2 Internally Connected Positive Power Supply Ground 6 2. BLOCK DIAGRAM * AN0-AN7 AVREF AVSS 8 A/D CONVERTER PORT 0 BASIC INTERVAL TIMER INTBT PROGRAM COUNTER (14) ALU CY PORT 3 BANK 4 P30-P33 SP(8) PORT 1 4 4 P00-P03 P10-P13 PORT 2 4 P20-P23 TI0/P13 PTO0/P20 TIMER/EVENT COUNTER #0 INTT0 PORT 4 4 4 TI1/P80 PTO1/P21 TIMER/EVENT COUNTER #1 INTT1 GENERAL REG. P40-P43 PORT 5 PORT 6 PORT 7 DATA MEMORY (RAM) 768 x 4 BITS P50-P53 P60-P63 4 4 BUZ/P23 WATCH TIMER PROGRAM MEMORY (ROM) 16256 x 8 BITS DECODE AND CONTROL P70-P73 INTW f LCD PORT 8 4 P80-P83 SI/SB1/P03 SO/SB0/P02 SCK/P01 CLOCKED SERIAL INTERFACE INTCSI 12 S12-S23 S24/BP0 -S31/BP7 COM0-COM3 8 INT0/P10 INT1/P11 INT2/P12 INT4/P00 KR0/P60 -KR3/P63 KR4/P70 -KR7/P73 8 INTERRUPT CONTROL fX / 2 CLOCK OUTPUT CONTROL CLOCK DIVIDER N SYSTEM CLOCK GENERATOR SUB MAIN LCD CONTROLLER /DRIVER STAND BY CONTROL CPU CLOCK fLCD 4 3 VLC0-VLC2 BIT SEQ. BUFFER (16) PCL/P22 XT1 XT2 X1 X2 VDD VSS RESET BIAS LCDCL/P30 SYNC/P31 PD75336 * AN6/P82, AN7/P83 7 PD75336 3. PIN FUNCTIONS 3.1 PORT PINS (1/2) Pin Name P00 P01 P02 P03 P10 P11 Input/Output Input Input/output Input/output Input/output DualFunction Pin INT4 SCK SO/SB0 SI/SB1 INT0 INT1 Function 8-Bit I/O Reset I/O Circuit Type *1 B 4-bit input port (PORT 0) Pull-up resistor can be used for P01 to P03 as a 3-bit unit by software. F -A x Input F -B M-C With noise elimination function Input P12 P13 P20 P21 Input/output P22 P23 P30 *2 P31 *2 Input/output P32 *2 P33 *2 -- -- PCL BUZ LCDCL SYNC INT2 TI0 PTO0 PTO1 4-bit input port (PORT 1) Pull-up resistor can be used as a 4-bit unit by software. x Input B -C 4-bit input/output port (PORT 2) Pull-up resistor can be used as a 4-bit unit by software. x Input E-B Programmable 4-bit input/output port (PORT 3) Input/output can be specified bit-wise. Pull-up resistor can be used as a 4-bit unit by software. x Input E-B P40 to P43 *2 Input/output -- N-ch open-drain 4-bit input/output port (PORT 4) On-chip pull-up resistor can be specified bitwise (mask option). Open-drain: 10 V withstand voltage N-ch open-drain 4-bit input/output port (PORT 5) On-chip pull-up resistor can be specified bitwise (mask option). Open-drain: 10 V withstand voltage High level (on-chip pull-up resistor) or high-impedance M P50 to P53 *2 Input/output -- High level (on-chip pull-up resistor) or highimpedance M * 1. : Schmitt triggered input 2. LED direct drive possible 8 PD75336 3.1 PORT PINS (2/2) Pin Name P60 P61 Input/Output DualFunction Pin KR0 KR1 Function 8-Bit I/O Reset I/O Circuit Type *1 Input/output P62 P63 P70 P71 Input/output P72 P73 P80 P81 Input/output P82 P83 BP0 BP1 Output BP2 BP3 BP4 BP5 Output BP6 BP7 S30 S31 S26 S27 S28 S29 AN6 AN7 S24 S25 KR6 KR7 TI1 -- KR2 KR3 KR4 KR5 Programmable 4-bit input/output port (PORT 6) Input/output can be specified bit-wise. Pull-up resistor can be used as a 4-bit unit by software. Input F -A 4-bit input/output port (PORT 7) Pull-up resistor can be used as a 4-bit unit by software. Input F -A E -E 4-bit input/output port (PORT 8) Pull-up resistor can be used as a 4-bit unit by software. x E-B Input Y-B 1-bit output port (BIT PORT) Also used as segment output pin. x *2 G-C * 1. : Schmitt triggered input 2. BP0 to BP7 select VLC1 as the input source. However, the output level depends on BP0 to BP7 and VLC1 external circuit. Example BP0 to BP7 are connected mutually within the PD75336 as shown below. Therefore, the output level of BP0 to BP7 is determined by the value of R1, R2 and R3. VDD R2 BP0 ON VLC1 R1 ON BP1 R3 PD75336 9 PD75336 3.2 NON-PORT PINS (1/2) Pin Name TI0 Input/Output DualFunction Pin P13 Function Reset I/O Circuit Type * B -C Input TI1 PTO0 Output PTO1 PCL BUZ SCK SO/SB0 Output Output Input/output Input/output P21 P22 P23 P01 P02 P80 P20 External event pulse input to timer/event counter Input E -E Timer/event counter output Input E-B Clock output Fixed frequency output (for buzzer or system clock trimming) Serial clock input/output Serial data output Serial bus input/output Serial data input Serial bus input/output Edge detection vectored interrupt input (both rising edge and falling edge detection effective) Clocked Input Input Input Input E-B E-B F -A F -B SI/SB1 Input/output P03 Input M -C INT4 Input P00 Input B INT0 Input INT1 INT2 KR0 to KR3 KR4 to KR7 X1 Input X2 XT1 XT2 RESET IC VDD VSS Input Input Input Input P10 P11 P12 P60 to P63 P70 to P73 Edge detection vectored interrupt input (detection edge selectable) Input Asynchronous B -C Edge detection testable input (rising edge detection) Asynchronous Input Input Input B -C F -A F -A Parallel falling edge detection testable input Parallel falling edge detection testable input Main system clock oscillation crystal/ceramic connection pin. For external clock, the external clock signal is input to X1 and its opposite phase is input to X2. Subsystem clock oscillation crystal connection pin. For external clock, the external clock signal is input to XT1 and XT2 is opened. XT1 can be used as a 1-bit input (test). System reset input Internally Connected. Connect the IC pin to VDD directly. Positive power supply GND potential -- -- -- -- -- Input -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- * : Schmitt triggered input 10 PD75336 3.2 NON-PORT PINS (2/2) Pin Name S12 to S23 S24 to S31 COM0 to COM3 VLC0 to VLC2 BIAS LCDCL *1 SYNC *1 AN0 to AN5 AN6 AN7 AVREF AVSS Input/Output Output Output Output Input Output Output Output DualFunction Pin -- BP0 to BP7 -- -- -- P30 P31 -- Segment signal output Segment signal output Common signal output Function Reset *2 *2 *2 -- *3 Input Input I/O Circuit Type G-A G-C G-B -- -- E-B E-B Y LCD drive power supply with on-chip split resistor (mask option) Externally mounted split resistor cut output Clock output for driving the externally extended driver Clock output for synchronizing the externally extended driver Input P82 P83 A/D converter analogs signal input Input Y-B Input -- -- -- A/D converter reference voltage input A/D converter GND potential -- -- Z Z * 1. Reserved pins for future system extension. They are used now only as P30 and P31 pins. 2. For each display output, VLCX is selected as the input source. S12 to S31 COM0 to COM2 COM3 Each display output : VLC1 : VLC2 : VLC0 level varies depending on each display output and VLCX external circuit. 3. Low level if there is an on-chip split resistor. High impedance if there is no on-chip split resistor. 11 PD75336 3.3 PIN INPUT/OUTPUT CIRCUITS Input/output circuits of PD75336 pins are shown in schematic form. TYPE A (For TYPE E-B) TYPE D (For TYPE E-B, F-A) VDD VDD data P-ch IN N-ch output disable N-ch P-ch OUT Push-pull output that can be made high-impedance output (PCMOS Standard Input Buffer TYPE B ch and N-ch OFF) TYPE E-B VDD P.U.R. P.U.R. enable IN P-ch data Type D output disable IN/OUT Type A P.U.R.:Pull-Up Resistor Schmitt-Triggered Input with Hysteresis Characteristic TYPE B-C TYPE E-E VDD P.U.R. VDD P.U.R. data P.U.R. enable P-ch IN/OUT Type D P-ch P.U.R. enable output disable Type A IN P.U.R. : Pull-Up Resistor Schmitt-Triggered Input with Hysteresis Characteristic Type B P.U.R.:Pull-Up Resistor 12 PD75336 TYPE F-A VDD TYPE G-B VLC0 P.U.R. P.U.R. enable P-ch VLC1 P-ch P-ch N-ch IN/OUT Type D data output disable OUT COM data N-ch VLC2 P-ch Type B N-ch P.U.R.:Pull-Up Resistor TYPE F-B VDD P.U.R. TYPE G-C VDD P.U.R. enable output disable (P) data output disable output disable (N) N-ch VDD P-ch P-ch VLC0 P-ch IN/OUT VLC1 P-ch SEG data/Bit Port data VLC2 N-ch OUT N-ch P.U.R.:Pull-Up Resistor TYPE G-A TYPE M P.U.R. enable Mask Opution VDD IN/OUT VLC0 P-ch VLC1 P-ch SEG data N-ch VLC2 N-ch Middle-High Voltage Input Buffer (+10 V Withstand Voltage) P.U.R.:Pull-Up Resistor data output disable N-ch OUT 13 PD75336 TYPE M-C TYPE Y-B VDD P.U.R. P.U.R. enable P-ch IN/OUT data Type D output disable P.U.R. enable VDD P-ch IN/OUT data output disable N-ch Type A port * input Type Y P.U.R.:Pull-Up Resistor P.U.R.:Pull-Up Resistor TYPE Y TYPE Z IN VDD IN P-ch N-ch VDD Sampling C + - Reference Voltage AVSS AVSS Reference Voltage (from Voltage Tap of Serial Resistor String) input enable AVSS * This becomes active in executing input instruction. 14 PD75336 3.4 MASK OPTION SELECTION The following mask options are available for the pins. Pin P40 to P43, P50 to P53 VLC0 to VLC2, BIAS XT1, XT2 1 1 Pull-up resistor not available (specifiable bit-wise) Split resistor available for LCD drive power supply (specifiable in 4 units) Feedback resistor available (when subsystem clock is used) Mask Option 2 2 Pull-up resistor available (specifiable bit-wise) Split resistor not available for LCD drive power supply (specifiable in 4 units) Feedback resistor not available (when subsystem clock is not used) 1 2 3.5 RECOMMENDED CONNECTION OF UNUSED PINS Pin P00/INT4 P01/SCK P02/SO/SB0 P03/SI/SB1 P10/INT0 to P12/INT2 P13/TI0 P20/PTO0 P21/PTO1 P22/PCL P23/BUZ P30 to P33 P40 to P43 P50 to P53 P60 to P63 P70 to P73 P80, P81 P82/AN6, P83/AN7 S12 to S23 S24/BP0 to S31/BP7 COM0 to COM3 VLC0 to VLC2 BIAS XT1 XT2 AN0 to AN5 IC Connect to VSS. Connect to VSS only when none of VLC0 to VLC2 are used. Leave open in all other cases. Connect to VSS or VDD. Leave open. Connect to VSS or VDD. Connect to VDD directly. Leave open. Input status : Connect to VSS or VDD. Output status: Leave open. Connect to VSS. Connect to VSS or VDD. Connect to VSS. Recommended Connection 15 PD75336 4. MEMORY CONFIGURATION * Program memory (ROM) ......16256 x 8 bits (0000H to 3F7FH) * 0000H, 0001H : Vector table for writing the program start address by restart * 0002H to 000DH : Vector table for writing the program start address by interrupt * 0020H to 007FH : Table area referred to by GETI instruction * Data memory * Data area ...768 x 4 bits (000H to 2FFH) *Peripheral hardware area ...128 x 4 bits (F80H to FFFH) 16 PD75336 Fig. 4-1 Program Memory Map Address 7 0000H MBE 6 RBE Reset Start Address (High-Order 6 Bits) Reset Start Address (Low-Order 8 Bits) 0 0002H MBE RBE INTBT/INT4 Start Address (High-Order 6 Bits) INTBT/INT4 Start Address (Low-Order 8 Bits) 0004H MBE RBE INT0 Start Address (High-Order 6 Bits) INT0 Start Address (Low-Order 8 Bits) 0006H MBE RBE INT1 Start Address (High-Order 6 Bits) INT1 Start Address (Low-Order 8 Bits) CALL !addr Instruction Subroutine Entry Address 0008H MBE RBE INTCSI Start Address (High-Order 6 Bits) INTCSI Start Address (Low-Order 8 Bits) 000AH MBE RBE INTT0 Start Address (High-Order 6 Bits) INTT0 Start Address (Low-Order 8 Bits) 000CH MBE RBE INTT1 Start Address (High-Order 6 Bits) INTT1 Start Address (Low-Order 8 Bits) CALLF ! faddr Instruction Entry Address BR !addr Instruction Branch Address BRCB ! caddr Branch Address BR $addr Instruction Relative Branch Address (-15 to -1, +2 to +16) 0020H GETI Instruction Reference Table 007FH 0080H 07FFH 0800H BRCB ! caddr Branch Address Branch Destination Address and Subroutine Entry Address by GETI Instruction 0FFFH 1000H 1FFFH 2000H 2FFFH 3000H BRCB ! caddr Branch Address 3F7FH BRCB ! caddr Branch Address Remarks Apart from the cases above, branching is possible to an address for which the PC low-order 8 bits only have been changed, by the BR PCDE or BR PCXA instruction. 17 PD75336 Fig. 4-2 Data Memory Map Data Memory 000H General Register Area 01FH 020H Stack Area (224 x 4) Data Area Static RAM (768 x 4) 0FFH 100H (236 x 4) 1EBH 1ECH Display Data Memory Area (20 x 4) 1FFH 200H (20 x 4) (32 x 4) Memory Bank Bank 0 Bank 1 256 x 4 Bank 2 2FFH Not Incorporated F80H Peripheral Hardware Area (128 x 4) FFFH 128 x 4 Bank 15 Remarks Banks 0, 1, 2 : 256 x 4 bits Bank 15 : 128 x 4 bits 18 PD75336 5. PERIPHERAL HARDWARE FUNCTIONS 5.1 PORTS :8 : 20 :8 : 8 44 Table 5-1 Port Functions Port (Symbol) Function Operation/Features Remarks Dual-function pins as SO/SB0, SI/ SB1, SCK, INT0 to INT2, INT4 and TI0 Dual-function pins as LCDCL and SYNC. Dual-function pins as KR0 to KR3. 4-bit input/output Can be set in the input or output mode as a 4bit unit. Port 6 and Port 7 are paired for input and output of data as an 8-bit unit. Dual-function pins as PTO0, PTO1, PCL and BUZ in port 2. Dual-function pins as KR4 to KR7. Dual-function pins as TI1, AN6 and AN7 4-bit input/output (N-ch open-drain 10 V withstand voltage) Can be set in the input or output mode as a 4bit unit. Port 4 and port 5 are paired for input and output of data as an 8-bit unit. Data are output bit-wise. Can be switched with LCD driver segment outputs S24 to S31 through software. In the case of the mask option, onchip pull-up resistors can be specified bit-wise. There are four types of I/O port as follows. * CMOS input (PORT0, 1) * CMOS input/output (PORT2, 3, 6, 7, 8) * CMOS output (BIT PORT) * N-ch open-drain input/output (PORT4, 5) Total PORT 0 PORT 1 4-bit input Regardless of the operating mode of the shared pin, reading or test is always possible. PORT 3 * PORT 6 Can be set in the input or output mode bit-wise PORT 2 PORT 7 PORT 8 PORT 4 * PORT 5 * BP0 to BP7 1-bit output * LED can be directly driven. 19 PD75336 5.2 CLOCK GENERATOR Clock generator operation is determined by the processor clock control register (PCC) and the system clock control register (SCC). There are two types of clock: main system clock and subsystem clock. The instruction execution time can also be changed. * 0.95 s/1.91 s/3.81 s/15.3 s (main system clock: at 4.19 MHz operation) * 122 s (subsystem clock: at 32.768 kHz operation) Fig. 5-1 Block Diagram of Clock Generator XT1 VDD XT2 X1 VDD X2 Main System Clock Oscillation Circuit fX 1/2 1/4 1/16 Subsystem Clock Oscillation Circuit fXT LCD Controller/ Driver Watch Timer * Basic Interval Timer (BT) * Timer/Event Counter * Serial Interface * Watch Timer * LCD Controller/Driver * A/D Converter * INT0 Noise Eliminator * Clock Output Circuit 1/8 to 1/4096 Frequency Divider WM. 3 SCC SCC3 Internal Bus Oscillation Stop Selector Selector Frequency Divider 1/4 SCC0 PCC PCC0 PCC1 4 HALT * STOP * PCC2, PCC3 Clear PCC2 PCC3 R * CPU * INT0 Noise Eliminator * Clock Output Circuit HALT F/F S Q STOP F/F Q S Wait Release Signal from BT RESET Signal R * Instruction execution 1. 2. 3. 4. 5. 6. fX = Main system clock frequency fXT = Subsystem clock frequency Standby Release Signal from Interrupt Control Circuit Remarks = CPU clock PCC: Processor clock control register SCC: System clock control register 1 clock cycle of (tCY) is 1 machine cycle of instruction. For tCY, refer to "AC CHARACTERISTICS" in 10. "ELECTRICAL SPECIFICATIONS". 20 PD75336 5.3 CLOCK OUTPUT CIRCUIT The clock output circuit is intended to output clock pulses from the P22/PCL pin and is used for remote control or to supply clock pulses to peripheral LSIs. * Clock output (PCL): , 524 kHz, 262 kHz, 65.5 kHz (at 4.19 MHz operation) Fig. 5-2 Clock Output Circuit Configuration From Clock Generator fX/2 fX/2 fX/2 3 Output Buffer Selector PCL/P22 4 6 PORT2.2 CLOM3 0 CLOM1CLOM0 CLOM P22 Output Latch Bit 2 of PMGB Bit Specified In Port 2 Input/Output Mode 4 Internal Bus Remarks The clock circuit is so configured that short-width pulses are not generated when clock output enable/disable is switched. 21 PD75336 5.4 BASIC INTERVAL TIMER The basic interval timer has the following functions: * * * * Interval timer operation to generate reference time interrupts Watchdog timer application to detect program runaway Wait time selection and count after the standby mode is released Count content read Fig. 5-3 Basic Interval Timer Configuration From Clock Generator fX/2 5 Clear Clear fX/2 7 MPX fX/2 fX/2 9 Basic Interval Timer (8-Bit Frequency Divider) Set BT Interrupt Request Flag 12 BT IRQBT Vectored Interrupt Request Signal 3 Wait Release Signal during Standby Release BTM3 BTM2 BTM1 BTM0 BTM SET1* 4 Internal Bus 8 * Instruction execution 22 PD75336 5.5 WATCH TIMER The PD75336 has one-channel on-chip watch timer. The watch timer has the following functions. * Sets the test flag (IRQW) at a 0.5 sec. time interval. Can release the standby mode by IRQW. * Can generate the 0.5 sec. time interval with the main system clock or the subsystem clock. * Can carry out program debugging or inspection efficiently in the fast feed mode with a time interval set to 3.91 s (128 times the normal feed mode). * Can generate a frequency of 2.048, 4.096 or 32.768 kHz to the P23/BUZ pin to generate buzzer sound or trim the system clock oscillation frequency. * Can start the watch at zero second since it can clear the divider. Fig. 5-4 Block Diagram of Watch Timer fW 6 2 (512 Hz : 1.95 ms) fLCD fW (256 Hz : 3.91 ms) 7 2 fX 128 (32.768 kHz) fXT (32.768 kHz) Selector INTW IRQW Set Signal fW (32.768 kHz) From Clock Generator Selector fW 14 2 Frequency Divider (4 kHz) (2 kHz) 2 Hz 0.5 sec Clear fW 3 2 fW 4 2 Selector Output Buffer P23/BUZ WM WM7 0 WM5 WM4 WM3 WM2 WM1 WM0 PORT2.3 P23 Output Latch Bit 2 of PMGB Port 2 Input/Output Mode 8 Bit Test Instruction Internal Bus Values in parentheses are when fX = 4.194304 MHz and fXT = 32.768 kHz. 23 PD75336 5.6 TIMER/EVENT COUNTER (1) Timer/event counter configuration The PD75336 has two channels of timer/event counters. Channels 0 and 1 of the timer/event counter have the following differences. Table 5-2 Differences between Timer/Event Counter Channel 0 and Channel 1 Differences Selection count pulse Clock supply to the serial interface Channel 0 fX/210, fX/28, fX/26, fX/24, Possible Channel 1 fX/212, fX/210, fX/28, fX/26 Impossible (2) Timer/event counter functions The timer/event counter functions are: * Programmable interval timer operation * Output of square wave having any selected frequency to the PTOn pin * * * * Event counter operation Output of N-divided TIn pin input to the PTOn pin (frequency divider operation) Serial shift clock supply to the serial interface circuit Count status call function 24 Fig. 5-5 Timer/Event Counter Block Diagram Internal Bus SET1 8 TMn6 TMn5 TMn4 TMn3 TMn2 *1 TMn 8 8 Modulo Register (8) TMODn TOEn TO Enable Flag PORT2.n Bit 2 of PGMB Port 2 P2n Input/ Output Output Latch Mode To Serial Interface PTOn Output Buffer INTTn IRQTn Set Signal Port Input Buffer 8 Comparator (8) 8 Tn MPX Count Register (8) CP Clear Timer Operation Start Match TOUT F/F Reset *2 Input Buffer TIn From Clock Generator RESET IRQTn Clear Signal Remarks n = 0, 1 (n indicates channel number) * 1. Instruction execution 2. Only from channel 0 of timer/event counter PD75336 25 PD75336 5.7 SERIAL INTERFACE The PD75336 incorporates a clocked 8-bit serial interface, with four modes available. * * * * Operation-halted mode 3-wire serial I/O mode 2-wire serial I/O mode SBI mode (serial bus interface mode) 26 Fig. 5-6 Serial Interface Block Diagram Internal Bus 8/4 Bit Test CSIM 8 8 8 Slave Address Register (SVA) Bit Manipulation (8) Match Signal (8) RELT CMDT SBIC Bit Test Addres Comparator P03/SI/SB1 Selector Shift Register (SIO) (8) SO SET CLR Latch D Q P02/SO/SB0 Selector Busy/ Acknowledge Output Circuit Bus Release/ Command/ Acknowledge Detection Circuit RELD CMDD ACKD P01/SCK ACKT ACKE BSYE Serial Clock Counter P01 Output Latch INTCSI Control Circuit IRQCSI Set Signal INTCSI Serial Clock Control Circuit Serial Clock Slector fX/24 fX/2 6 fX/2 TOUT F/F (From Timer/ Event Counter 0) External SCK 3 PD75336 27 PD75336 5.8 LCD CONTROLLER/DRIVER The PD75336 incorporates a display controller which generates a segment signal and a common signal in accordance with the display data memory and a segment drive and a common driver which can directly operate the LCD panel. The LCD controller/driver has the following functions. * Automatically read display data memory by DMA operation and generates segment and common signals. * Can select one of the following 5 display modes. 1 2 3 4 Static 1/2 duty (2-time multiplexing), 1/2 bias 1/3 duty (3-time multiplexing), 1/2 bias 1/3 duty (3-time multiplexing), 1/3 bias 5 1/4 duty (4-time multiplexing), 1/3 bias * Can select one of the four frame frequencies in each display mode. * Has a maximum of 20 segment signal outputs (S12 to S31) and a maximum of 4 common outputs (COM0 to COM3). * The segment outputs (S24 to S27, S28 to S31) can be switched to output ports in 4 output units (BP0 to BP3, BP4 to BP7). * Can incorporate a split resistor for LCD drive power supply (mask option). * Applicable to various types of bias methods and LCD drive voltage. * Cuts off current to the split resistor when display is off. * The display data memory not used for display can be used as a normal data memory. * Can operate with subsystem clock. 28 Fig. 5-7 LCD Controller/Driver Block Diagram 4 Display Data Memory 1FFH 3 2 1 0 3 1FEH 2 1 0 3 1F9H 2 1 0 3 1F8H 2 1 0 1ECH 32 10 8 Display Mode Register 4 Display Control Register 4 Port 3 Output Latch 10 8 Port Mode Register Group A 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 32 10 Timing Controller fLCD Multiplexer Selector Segment Driver Common Driver LCD Driver Voltage Control S31/PB7 S30/BP6 S24/BP0 S23 S12 COM3 COM2COM1COM0 V LC2 VLC1 VLC0 P31/ P30/ SYNC LCDCL PD75336 29 PD75336 5.9 A/D CONVERTER The PD75336 incorporates an 8-bit resolution analog/digital (A/D) converter having 8-channel analog inputs (AN0 to AN7). The A/D converter employs the successive approximation method. Fig. 5-8 A/D Converter Block Diagram Internal Bus ADM 0 ADM6 ADM5 ADM4 SOC EOC 0 0 8 AN0 AN1 Sample & Hold Circuit AN2 AN3 Multiplexer AN4 AN5 AN6/P82 AN7/P83 Control Circuit + - Comparator SA Register (8) 8 Tap Decoder AVREF R/2 R R R R/2 Serial Resistor String AVSS 30 PD75336 5.10 BIT SEQUENTIAL BUFFER.....16 BIT The bit sequential buffer 0 to 3 (BSB0 to BSB3) is a special data memory for bit manipulation. Since it can carry out bit manipulation easily by sequentially changing the address and bit specification, the bit sequential buffer is useful to process data having a long bit length bit-wise. Fig. 5-9 Bit Sequential Buffer Format Address Bit Symbol 3 2 FC3H 1 BSB3 0 3 2 FC2H 1 BSB2 0 3 2 FC1H 1 0 3 2 FC0H 1 0 BSB0 BSB1 L Register L = F L=CL=B INCS L L=8L=7 DECS L L=4 L=3 L=0 Remarks 1. 2. In pmem.@L addressing, the specified bit shifts in accordance with the L register. In pmem.@L addressing, BSB is always operable regardless of MBE, MBS specifications. 31 PD75336 6. INTERRUPT FUNCTIONS The PD75336 has seven types of interrupt sources enabling multiplex interruption by the software control. It has also two types of test source. INT2 of the test source is equipped with two types of edge detection testable inputs. The PD75336 interrupt control circuit has the following functions: * Vectored interrupt function controlled by the hardware which can control enabling/disabling of interrupt acknowledge using interrupt flag (IExxx) and interrupt master enable flag (IME) * Function of setting any interrupt start address * Multiplex interruption function capable of specifying priority using the interrupt priority select register (IPS) * Interrupt request flag (IRQxxx) test function (generation of interrupt can be checked by the software) * Standby mode release function (interrupt to be released can be selected using the interrupt enable flag) 32 Fig. 6-1 Block Diagram Interrupt Control Circuit Internal Bus 2 IM2 1 IM1 3 IM0 Interrupt Enable Flag (IEXXX) IME IPS IST0 INT BT INT4 /P00 INT0 /P10 INT1 /P11 Both Edges Detection Circuit Decoder IRQBT IRQ4 IRQ0 IRQ1 IRQCSI IRQT0 IRQT1 IRQW Selector VRQn * Edge Detection Circuit Edge Detection Circuit Priority Control Circuit INTCSI INTT0 INTT1 INTW INT2 /P12 KR0/P60 KR7/P73 Rising Edge Detection Circuit Falling Edge Detection Circuit Vector Table Address Generator IRQ2 Standby Release Signal IM2 * Noise Eliminator PD75336 33 PD75336 7. STANDBY FUNCTIONS Two standby modes (STOP mode and HALT mode) are available for the PD75336 to reduce power consumption during standby for program. Table 7-1 Operating Status in Standby Mode Item Setting instruction Mode STOP Mode STOP instruction HALT Mode HALT instruction Main system clock or subsystem clock settable Only CPU clock stopped (oscillation continued) Operable only with main system clock oscillation (IRQBT set at reference time intervals) Operable with main system clock oscillation or when external SCK input is selected as serial clock. Operable with main system clock oscillation or T10 and TI1 pin input specified as count clock. System clock at setting Only main system clock settable Clock generator Only main system clock oscillation stopped Basic interval timer Operation stop Serial interface Operable only when external SCK input selected as serial clock Operation Status Timer/event counter Operable only when TI0 and TI1 pin input specified as count clock Watch timer Operable only when fXT selected as count clock Operable only when fXT selected as LCDCL Operable LCD controller Operable A/D converter Operation stop Operable * External interrupt INT1, 2, 4: Operable Only INT0 inoperable Operation stop Interrupt request signal from operable hardware enabled by interrupt enable flag, or RESET input Interrupt request signal from operable hardware enabled by interrupt enable flag, or RESET input CPU Release signal * Operation possible only during main system clock oscillation 34 PD75336 8. RESET FUNCTIONS The PD75336 is set by RESET input and each hardware is initialized as shown in Table 8-1. Reset operation timing is shown in Fig. 8-1. Fig. 8-1 Reset Operation by RESET Input Wait (31.3 ms/4.19 MHz) RESET Input Operating Mode or Standby Mode HALT Mode Operating Mode Internal Reset Operation 35 PD75336 Table 8-1 Status after Reset of Each Hardware (1/2) Hardware RESET Input in Standby Mode Low-order 6 bits of program memory address 0000H are set to PC13 to PC8 and the contents of address 0001H are set in PC7 to PC0. Held 0 0 Bit 6 of program memory address 0000H is set in RBE, and bit 7 is set to MBE. Undefined Held* Held 0, 0 Undefined 0 0 FFH 0 0, 0 0 Held 0 0 Held 0 0 0 0 0 04H (EOC = 1) 7FH RESET Input during Operation Low-order 6 bits of program memory address 0000H are set to PC13 to PC8 and the contents of address 0001H are set in PC7 to PC0. Undefined 0 0 Bit 6 of program memory address 0000H is set in RBE, and bit 7 is set to MBE. Undefined Undefined Undefined 0, 0 Undefined 0 0 FFH 0 0, 0 0 Undefined 0 0 Undefined 0 0 0 0 0 04H (EOC = 1) 7FH Program counter (PC) Carry flag (CY) Skip flag (SK0 to SK2) PSW Interrupt status flag (IST0) Bank enable flag (MBE, RBE) Stack pointer (SP) Data memory (RAM) General register (X, A, H, L, D, E, B, C) Bank selection register (MBS, RBS) Basic interval timer Counter (BT) Mode register (BTM) Counter (Tn) Timer/event counter (n = 0, 1) Modulo register (TMODn) Mode register (TMn) TOEn, TOUT F/F Watch timer Mode register (WM) Shift register (SIO) Operating mode register (CSIM) Serial interface SBI control register (SBIC) Slave address register (SVA) Processor clock control register (PCC) Clock generator, clock output circuit System clock control register (SCC) Clock output mode register (CLOM) Display mode register (LCDM) LCD controller Display control register (LCDC) Mode register (ADM), EOC A/D converter SA register * 36 Data of data memory addresses 0F8H to 0FDH becomes undefined by RESET input. PD75336 Table 8-1 Status after Reset of Each Hardware (2/2) Hardware RESET Input in Standby Mode IRQ1, IRQ2, IRQ4 Other than above RESET Input during Operation Undefined 0 0 0 0, 0, 0 OFF Clear (0) 0 0 Interrupt request flag (IRQxxx) Interrupt function Undefined 0 0 0 0, 0, 0 OFF Clear (0) 0 0 5 Interrupt enable flag (IExxx) Priority select register (IPS) INT0, 1, 2 mode registers (IM0, IM1, IM2) Output buffer Output latch Digital port I/O mode register (PMGA, PMGB, PMGC) Pull-up resistor specification register (POGA, POGB) P00 P20 P60 P80 to to to to P03, P10 to P13, P23, P30 to P33, P63, P70 to P73, P83 Input Input P40 to P43, P50 to P53 Pin status S12 to S31, COM0 to COM3 * High level: With an on-chip pull-up resistor * High impedance: In open-drain * High level: With an on-chip pull-up resistor * High impedance: In open-drain * * Low level: With an on-chip split resistor * High impedance: Without an on-chip split resistor Held * * Low level: With an on-chip split resistor * High impedance: Without an on-chip split resistor Undefined BIAS Bit sequential buffer (BSB0 to BSB3) * Each display output selects the following VLCX as input source. S12 to S31: VLC1 COM0 to COM2: VLC2 COM3: VLC0 However, the level of each display output varies depending on each display output and VLCX external circuit. 37 PD75336 9. INSTRUCTION SET (1) Operand representation and description methods In the operand column of each instruction, operands are entered in accordance with the description method for the operand representation of the instruction (refer to RA75X Assembler Package User's Manual Language Volume (EEU-730) for details). If there is more than one description method, select one method. Alphabetic capital letters, plus and minus signs are keywords. Describe them what they are. In the case of immediate data, describe appropriate numeric values or labels. Symbols of various registers and flags can be described as labels in place of mem, fmem, pmem, bit, etc. (Refer to PD75336 User's Manual (IEU-725) for details.) However, labels which can be written for fmem and pmem are limited. Identifier reg reg1 rp rp1 rp2 rp' rp'1 rpa rpa1 n4 n8 mem bit fmem pmem addr caddr faddr taddr PORTn IExxx RBn MBn X, A, B, C, D, E, H, L X, B, C, D, E, H, L Description XA, BC, DE, HL BC, DE, HL BC, DE XA, BC, DE, HL, XA', BC', DE', HL' BC, DE, HL, XA', BC', DE', HL' HL, HL+, HL-, DE, DL DE, DL 4-bit immediate data or label 8-bit immediate data or label 8-bit immediate data or label * 2-bit immediate data or label FB0H to FBFH, FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label 0000H to 3F7FH immediate data or label 12-bit immediate data or label 11-bit immediate data or label 20H to 7FH immediate data (however, bit0 = 0) or label PORT 0 to PORT 8 IEBT, IET0, IET1, IE0 to IE2, IE4, IECSI, IEW RB0 to RB3 MB0, MB1, MB2, MB15 * Only even address can be entered for mem in 8-bit data processing. 38 PD75336 (2) Operation description legend A : A register; 4-bit accumulator B : B register; 4-bit accumulator C D E H L X XA BC DE HL XA' BC' DE' HL' PC SP CY PSW MBE RBE PORTn IME IPS IExxx RBS MBS PCC * (xx) xxH : : : : : : : : : : : : : : : : : : : : : : : : : : : : C register; 4-bit accumulator D register; 4-bit accumulator E register; 4-bit accumulator H register; 4-bit accumulator L register; 4-bit accumulator X register; 4-bit accumulator Register pair (XA); 8-bit accumulator Register pair (BC) Register pair (DE) Register pair (HL) Expanded register Expanded register Expanded register Expanded register Program counter Stack pointer pair pair pair pair (XA') (BC') (DE') (HL') Carry flag; bit accumulator Program status word Memory bank enable flag Register bank enable flag Portn (n = 0 to 8) Interrupt master enable flag Interrupt priority select register Interrupt enable flag Register bank select register Memory bank select register Processor clock control register Address, bit delimiter : Contents addressed by xx : Hexadecimal data 39 PD75336 (3) Description of symbols in the addressing area column *1 *2 *3 MB = MBE * MBS (MBS = 0, 1, 2, 15) MB = 0 MBE = 0 : MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) MBE = 1 : MB = MBS (MBS = 0, 1, 2, 15) MB = 15, fmem = FB0H to FBFH, FF0H to FFFH MB = 15, pmem = FC0H to FFFH addr = 0000H to 3F7FH addr = (Current PC) -15 to (Current PC) -1 (Current PC) + 2 to (Current PC) + 16 caddr = 0000H 1000H 2000H 3000H to to to to 0FFFH 1FFFH 2FFFH 3F7FH (PC13, 12 = (PC13, 12 = (PC13, 12 = (PC13, 12 = 00B) or 01B) or 10B) or 11B) Program memory addressing Data memory addressing *4 *5 *6 *7 *8 *9 *10 faddr = 0000H to 07FFH taddr = 0020H to 007FH Remarks 1. 2. 3. 4. MB indicates an accessible memory bank. In *2, MB = 0 irrespective of MBE and MBS. In *4 and *5, MB = 15 irrespective of MBE and MBS. *6 to *10 indicate addressable areas. (4) Description of machine cycle column S indicates the number of machine cycles required for an instruction with skip function to carry out skip operation. The value of S varies as follows: * When not skipped ................................................................................................................................... * When the skipped instruction is a 1-byte or 2-byte instruction ....................................................... * When the skipped instruction is a 3-byte instruction (BR !adder, CALL !adder instructions) ..... Note GETI instruction is skipped in a 1 machine cycle. S=0 S=1 S=2 The 1 machine cycle is equal to one cycle of CPU clock (=tCY) and four time periods are selectable by setting the PCC. 40 PD75336 Note 1 Mnemonic Operands A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL- Bytes 1 2 2 2 2 1 1 1 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1 2 2 2 1 2 1 1 Machine Cycles 1 2 2 2 2 1 2+S 2+S 1 2 1 2 2 2 2 2 2 2 2 2 1 2+S 2+S 1 2 2 2 1 2 3 3 A n4 reg1 n4 XA n8 HL n8 rp2 n8 A (HL) Operation Addressing Area Skip Condition Stack A Stack A Stack B *1 *1 *1 *2 *1 *1 *1 *3 *3 *3 *3 L=0 L = FH A (HL), then L L + 1 A (HL), then L L - 1 A (rpa1) XA (HL) (HL) A (HL) XA A (mem) XA (mem) (mem) A (mem) XA A reg XA rp' reg1 A rp'1 XA A (HL) A (HL), then L L + 1 A (HL), then L L - 1 A (rpa1) XA (HL) A (mem) XA (mem) A reg1 XA rp' XA (PC13-8 + DE)ROM XA (PC13-8 + XA)ROM MOV A, @rpa1 XA, @HL @HL, A @HL, XA A, mem Transfer XA, mem mem, A mem, XA A, reg XA, rp' reg1, A rp'1, XA A, @HL A, @HL+ A, @HL- A, @rpa1 XCH XA, @HL A, mem XA, mem A, reg1 XA, rp' *1 *1 *1 *2 *1 *3 *3 L=0 L = FH Note 2 MOVT XA, @PCDE XA, @PCXA Note 1. Instruction Group 2. Table reference 41 PD75336 Note 1 Mnemonic Operands Bytes Machine Cycles 2 2 2 2 2 2 1+S 2+S 1+S 2+S 2+S 1 2 2 1+S 2+S 2+S 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 Operation CY (fmem.bit) CY (pmem7-2 + L3-2.bit(L1-0)) CY (H + mem3-0 .bit) (fmem.bit) CY (pmem7-2 + L3-2.bit(L1-0)) CY (H + mem3-0 .bit) CY A A + n4 XA XA + n8 A A + (HL) XA XA + rp' rp'1 rp'1 + XA A, CY A + (HL) + CY XA, CY XA + rp' + CY rp'1, CY rp'1 + XA + CY A A - (HL) XA XA - rp' rp'1 rp'1 - XA A, CY A - (HL) - CY XA, CY XA - rp' - CY rp'1, CY rp'1 - XA - CY A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA A A n4 A A (HL) XA XA rp' rp'1 rp'1 XA Addressing Area *4 *5 *1 *4 *5 *1 Skip Condition CY, fmem.bit Bit transfer CY, pmem.@L MOV1 CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY A, #n4 XA, #n8 ADDS A, @HL XA, rp' rp'1, XA A, @HL ADDC XA, rp' rp'1, XA A, @HL SUBS XA, rp' rp'1, XA Operation A, @HL SUBC XA, rp' rp'1, XA A, #n4 AND A, @HL XA, rp' rp'1, XA A, #n4 OR A, @HL XA, rp' rp'1, XA A, #n4 XOR A, @HL XA, rp' rp'1, XA 2 2 2 2 2 2 1 2 1 2 2 1 2 2 1 2 2 1 2 2 2 1 2 2 2 1 2 2 2 1 2 2 carry carry *1 carry carry carry *1 *1 borrow borrow borrow *1 *1 *1 *1 Note Instruction Group 42 PD75336 Note 1 Increment/decrement Note 2 Mnemonic RORC NOT A A Operands Bytes Machine Cycles 1 2 1+S 1+S 2+S 2+S 1+S 2+S 2+S 2+S 1+S 2+S 2+S 2+S 1 1 1+S 1 Operation CY A0, A3 CY, An-1 An AA reg reg + 1 rp1 rp1 + 1 (HL) (HL) + 1 (mem) (mem) + 1 reg reg - 1 rp' rp' - 1 Skip if reg = n4 Skip if (HL) = n4 Skip if A = (HL) Skip if XA = (HL) Skip if A = reg Skip if XA = rp' CY 1 CY 0 Skip if CY = 1 CY CY Addressing Area Skip Condition 1 2 1 1 2 2 1 2 2 2 1 2 2 2 1 1 1 1 reg INCS rp1 @HL mem DECS reg rp' reg, #n4 reg = 0 rp1 = 00H *1 *3 (HL) = 0 (mem) = 0 reg = FH rp' = FFH reg = n4 *1 *1 *1 (HL) = n4 A = (HL) XA = (HL) A = reg XA = rp' Comparison @HL, #n4 SKE A, @HL XA, @HL A, reg XA, reg SET1 CY CY CY CY Note 3 CLR1 SKT NOT1 CY = 1 Note 1. Instruction Group 2. Accumulator operation 3. Carry flag operation 43 PD75336 Note Mnemonic Operands Machine Bytes Cycles 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2+S 2 2 2 2 2 2 2 2 2 (mem.bit) 1 (fmem.bit) 1 Operation Addressing Area *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *3 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 *4 *5 *1 Skip Condition mem.bit fmem.bit SET1 pmem.@L @H + mem.bit mem.bit fmem.bit CLR1 pmem.@L @H + mem.bit mem.bit fmem.bit SKT pmem.@L Memory bit manipulation @H + mem.bit mem.bit SKF fmem.bit pmem.@L @H + mem.bit fmem.bit SKTCLR pmem.@L @H + mem.bit CY, fmem.bit AND1 CY, pmem.@L CY, @H + mem.bit (pmem7-2 + L3-2.bit (L1-0)) 1 (H + mem3-0.bit) 1 (mem.bit) 0 (fmem.bit) 0 (pmem7-2 + L3-2.bit (L1-0)) 0 (H + mem3-0.bit) 0 Skip if (mem.bit) = 1 Skip if (fmem.bit) = 1 Skip if (pmem7-2 + L3-2.bit (L1-0)) = 1 Skip if (H + mem3-0.bit) = 1 Skip if (mem.bit) = 0 Skip if (fmem.bit) = 0 Skip if (pmem7-2 + L3-2.bit (L1-0)) = 0 Skip if (H + mem3-0.bit) = 0 Skip if (fmem.bit) = 1 and clear Skip if (pmem7-2 + L3-2.bit (L1-0)) = 1 and clear Skip if (H + mem3-0.bit) = 1 and clear CY CY (fmem.bit) CY CY (pmem7-2 + L3-2.bit (L1-0)) CY CY (H + mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2 + L3-2.bit (L1-0)) CY CY (H + mem3-0.bit) CY CY (fmem.bit) CY CY (pmem7-2 + L3-2.bit (L1-0)) CY CY (H + mem3-0.bit) PC13-0 addr (The assembler selects the optimum instruction from among the BR !addr, BRCB !caddr, and BR $addr instructions.) PC13-0 addr PC13-0 addr PC13-0 PC13-8 + DE PC13-0 PC13-8 + XA PC13-0 PC13,12 + caddr11-0 (mem.bit) = 1 (fmem.bit) = 1 (pmem.@L) = 1 (@H + mem.bit) = 1 (mem.bit) = 0 (fmem.bit) = 0 (pmem.@L) = 0 (@H + mem.bit) = 0 (fmem.bit) = 1 (pmem.@L) = 1 (@H + mem.bit) = 1 CY, fmem.bit OR1 CY, pmem.@L CY, @H + mem.bit CY, fmem.bit XOR1 CY, pmem.@L CY, @H + mem.bit addr -- -- *6 Branch BR !addr $addr PCDE PCXA 3 1 2 2 2 3 2 3 3 2 *6 *7 BRCB !caddr *8 Note Instruction Group 44 PD75336 Mnemonic Machine Cycles Addressing Area Note 1 Operands Bytes Operation Skip Condition CALL !addr 3 2 (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, RBE, PC13, PC12 PC13-0 addr, SP SP - 4 (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, RBE, PC13, PC12 PC13-0 000 + faddr, SP SP - 4 PC11-0 (SP) (SP + 3) (SP + 2) MBE, RBE, PC13, PC12 (SP + 1) SP SP + 4 PC11-0 (SP) (SP + 3) (SP + 2) MBE, RBE, PC13, PC12 (SP + 1) SP SP + 4, then skip unconditionally PC11-0 (SP) (SP + 3) (SP + 2) MBE, RBE, PC13, PC12 (SP + 1) PSW (SP + 4) (SP + 5), SP SP + 6 (SP - 1) (SP - 2) rp, SP SP - 2 (SP - 1) MBS, (SP - 2) RBS, SP SP - 2 rp (SP + 1) (SP), SP SP + 2 MBS (SP + 1), RBS (SP), SP SP + 2 IME(IPS.3) 1 IE x x x 1 IME(IPS.3) 0 IE x x x 0 A PORTn XA PORTn+1, PORTn PORTn A PORTn+1, PORTn XA Set HALT Mode (PCC.2 1) Set STOP Mode (PCC.3 1) No Operation RBS n MBS n (n = 0 - 3) (n = 0, 1, 2, 15) (n = 0-8) (n = 4, 6) (n = 2-8) (n =4, 6) *6 CALLF Subroutine stack control !faddr 2 2 *9 RET 1 3 RETS 1 3+S Unconditional RETI rp PUSH BS rp POP BS 1 3 1 2 1 2 2 1 2 1 2 2 2 2 2 2 2 2 2 2 2 1 2 2 Note 2 EI IE x x x 2 2 DI Input/output IE x x x A, PORTn XA, PORTn 2 2 2 2 2 2 2 1 IN* OUT* HALT STOP NOP PORTn, A PORTn, XA Note 3 RBn SEL MBn 2 2 GETI taddr 1 3 * TBR Instruction PC13-0 (taddr) 5-0 + (taddr + 1) ----------------------------------------------------------------------* TCALL Instruction (SP - 4) (SP - 1) (SP - 2) PC11-0 (SP - 3) MBE, RBE, PC13, PC12 PC13-0 (taddr) 5-0 (taddr + 1) SP SP - 4 ----------------------------------------------------------------------* Other than TBR and TCALL Instruction Execution of an instruction addressed at (taddr) and (taddr + 1) ----------------------------- Special *10 ----------------------------Depends on the referred instruction * At IN/OUT instruction execution, MBE = 0 or MBE = 1, MBS =15 must be set in advance. Remarks TBR and TCALL instructons are assembler pseudo instructions for GETI instruction table definition. Note 1. Instruction Group 2. Interrupt control 3. CPU control 45 PD75336 10. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (Ta = 25 C) PARAMETER Power supply voltage SYMBOL VDD VI1 Input voltage VI2 Ports 4 and 5 Open-drain Output voltage VO One pin Output current high IOH All pins Peak value One pin rms Peak value Output current low IOL* Total of ports 0, 2, 3, 5 and 8 rms Peak value Total of ports 4, 6, and 7 rms Storage temperature Tstg 60 -65 to +150 mA C 60 100 mA mA 15 100 mA mA -30 30 mA mA -0.3 to +11 -0.3 to VDD +0.3 -15 V V mA Except ports 4 and 5 On-chip pull-up resistor TEST CONDITIONS RATING -0.3 to +7.0 -0.3 to VDD +0.3 -0.3 to VDD +0.3 UNIT V V V * Rms is calculated using the following expression: [rms] = [peak value] x duty Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter or even momentarily. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. 5 Note 5 GUARANTEED OPRERATING RANGE PARAMETER Power supply voltage Operating temperature SYMBOL VDD Topt TEST CONDITIONS MIN. 2.7 -40 TYP. MAX. 6.0 +85 UNIT V C CAPACITANCE (Ta = 25 C, VDD = 0 V) PARAMETER Input capacitance Output capacitance I/O capacitance SYMBOL CIN COUT CIO f = 1 MHz Unmeasured pins returned to 0 V. TEST CONDITIONS MIN. TYP. MAX. 15 15 15 UNIT pF pF pF 46 PD75336 MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) RESONATOR RECOMMENDED CIRCUIT PARAMETER Oscillator frequency (fx)*1 TEST CONDITIONS MIN. TYP. MAX. UNIT 1.0 After VDD reaches the MIN. value of the oscillation voltage range 1.0 VDD = 4.5 to 6.0 V 4.19 5.0*3 MHz X1 X2 Ceramic resonator C1 C2 Oscillation stabilization time*2 4 ms VDD Oscillator frequency (fx)*1 X1 X2 5.0*3 MHz Crystal resonator C1 C2 10 ms Oscillation stabilization time*2 30 ms VDD X1 X2 X1 input frequency (fx)*1 1.0 5.0*3 MHz External clock PD74HCU04 X1 input high-/low-level width (tXH, tXL) 100 500 ns * 1. The oscillator frequency and X1 input frequency indicate only the oscillator characteristics. For the instruction execution time refer to the AC CHARACTERISTICS. 2. The oscillation stabilization time is necessary for oscillation to stabilize after VDD reaches the MIN. value of the oscillation voltage range or releasing the STOP mode. 3. When the oscillator frequency is "4.19 MHz < fX 5.0 MHz" PCC = 0011 should for the instruction execution time. If PCC = 0011 is selection, 1 machine cycle is less than 0.95 s with the result that the specified MIN. value, 0.95 s cannot be observed. Note When using the main system clock oscillator or the subsystem clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines or not be placed close to a varying high current. * The potential of the oscillator capacitor ground should always be the same as VSS. Do not ground wiring to a ground pattern in which a high current flows. * Do not fetch a signal from the oscillator. The subsystem clock oscillator is a circuit with a low amplification level, more prone to misoperation due to noise than the main system clock. Therefore, when using the subsystem clock, special care is required in wiring methods. 5 47 PD75336 SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) RESONATOR RECOMMENDED CIRCUIT PARAMETER TEST CONDITIONS MIN. TYP. MAX. UNIT XT1 XT2 R Oscillator frequency (fXT)*1 VDD = 4.5 to 6.0 V Oscillation stabilization time*2 32 32.768 35 kHz Crystal resonator C3 1.0 2 s C4 10 VDD s XT1 input frequency (fXT)*1 XT1 XT2 Leave Open 32 100 kHz External clock XT1 input high-/ low-level width (tXTH,tXTL) 5 15 s * 1. The oscillator frequency and X1 input frequency indicate only the oscillator characteristics. For the instruction execution time refer to the AC CHARACTERISTICS. 2. The oscillation stabilization time is necessary for oscillation to stabilize after VDD reaches the MIN. value of the oscillation voltage range or releasing the STOP mode. When using the main system clock oscillator or the subsystem clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. * Wiring should be as short as possible. * Wiring should not cross other signal lines or not be placed close to a varying high current. * The potential of the oscillator capacitor ground should always be the same as VSS. Do not ground wiring to a ground pattern in which a high current flows. * Do not fetch a signal from the oscillator. The subsystem clock oscillator is a circuit with a low amplification level, more prone to misoperation due to noise than the main system clock. Therefore, when using the subsystem clock, special care is required in wiring methods. 5 Note 48 PD75336 DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) (1/2) PARAMETER SYMBOL VIH1 VIH2 Input voltage high VIH3 Ports 4 and 5 Open-drain VIH4 VIL1 Input voltage low VIL2 VIL3 X1, X2, XT1 Ports 2, 3, 4, 5 and 8 Ports 0, 1, 6, 7, RESET X1, X2, XT1 VDD = 4.5 to 6.0 V IOH = -1 mA IOH = -100 A VDD = 4.5 to 6.0 V IOH = -100 A IOH = -50 A Ports 3, 4 and 5 VDD = 4.5 to 6.0 V IOL = 15 mA Ports 0, 2, 3, 4, 5, 6, 7 and 8 VOL1 Output voltage low SB0, SB1 VDD = 4.5 to 6.0 V IOL = 1.6 mA IOL = 400 A Open-drain pull-up resistor 1 k VDD = 4.5 to 6.0 V IOL = 100 A IOL = 50 A Other than below VIN = VDD Input leakage current high ILIH2 ILIH3 ILIL1 VIN = 0 V ILIL2 ILOH1 Output leakage current high ILOH2 VOUT = VDD VOUT = 10 V X1, X2, XT1 Other than below Ports 4 and 5 (open-drain) -20 3 20 VIN = 10 V X1, X2, XT1 Ports 4 and 5 (open-drain) Other than below 20 20 -3 0.7 VDD VDD -0.5 0 0 0 VDD -1.0 VDD -0.5 VDD -2.0 VDD -1.0 10 VDD 0.3 VDD 0.2 VDD 0.4 V V V V V V V V V TEST CONDITIONS Ports 2, 3 and 8 Ports 0, 1, 6, 7, RESET On-chip pull-up resistor MIN. 0.7 VDD 0.8 VDD 0.7 VDD TYP. MAX. VDD VDD VDD UNIT V V V VOH1 Output voltage high VOH2 Ports 0, 2, 3, 6, 7, 8 BIAS BP0 to BP7 (with 2 IOH outputs) 0.4 2.0 V 0.4 0.5 0.2 VDD V V V VOL2 BP0 to BP7 (with 2 IOL outputs) 1.0 1.0 3 V V ILIH1 A A A A A A A A Input leakage current low Output leakage current low ILOL VOUT = 0 V -3 49 PD75336 DC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) (2/2) PARAMETER SYMBOL TEST CONDITIONS Ports 0, 1, 2, 3, 6, 7 and 8 (Except P00) VIN = 0 V Ports 4 and 5 VOUT = VDD -2.0 V VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% MIN. 15 30 15 10 2.5 60 IO = 5 A 100 40 TYP. 40 MAX. 80 300 70 60 VDD 140 0.2 UNIT k k k k V k RL1 On-chip pull-up resistor RL2 LCD drive voltage LCD split resistor LCD output voltage deviation*1 (common) LCD output voltage deviation*1 (segment) VLCD RLCD VODC VODS IO = 1 A VLCD0 = VLCD VLCD1 = VLCD x 2/3 VLCD2 = VLCD x 1/3 2.7 V VLCD VDD 0 V 0 0.2 V VDD = 5 V 10%*4 IDD1 4.19 MHz*3 crystal oscillation C1 = C2 = 22 pF IDD2 VDD = 3 V 10%*5 HALT mode Operating mode 2.5 0.35 500 150 30 8 1.2 1500 450 90 mA mA VDD = 5 V 10% VDD = 3 V 10% VDD = 3 V 10% VDD = 3 V 10% A A A A A A A Supply current*2 IDD3 32 kHz*6 crystal oscillation IDD4 HALT mode 5 0.5 0.1 15 20 10 5 VDD = 5 V 10% IDD5 XT1 = 0 V STOP mode VDD = 3 V 10% Ta = 25 C 0.1 * 1. The voltage deviation is the difference between the output voltage and the segment or common output desired value (VLCDn; n = 0, 1, 2) 2. Current which flows in the on-chip pull-up resistor or LCD split resistor is not included. 3. Including oscillation of the subsystem clock. 4. When the processor clock control register (PCC) is set to 0011 and the device is operated in the high-speed mode. 5. When PCC is set to 0000 and the device is operated in the low-speed mode. 6. When the system clock control register (SCC) is set to 1011 and the device is operated on the subsystem clock, with main system clock oscillation stopped. 50 PD75336 A/D CONVERTER CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V) PARAMETER Resolution 2.5 V AVREF VDD -10 Ta +85 C -40 Ta < -10 C SYMBOL TEST CONDITIONS MIN. 8 TYP. 8 MAX. 8 1.5 2.0 168/fX 44/fX AVSS 1000 1.0 2.0 AVREF LSB UNIT bit Absolute accuracy *1 Conversion time Sampling time Analog input voltage Analog Input impedance AVREF current tCONV tSAMP VIAN RAN IREF *2 *3 s s V M mA * 1. Absolute accuracy excluding quantization (1/2 LSB) error. 2. Time up to end of conversion (EOC = 1) after execution of the conversion start instruction. (40.1 s: fX = 4.19 MHz operation) 3. Time up to end of sampling after execution of the conversion start instruction. (10.5 s: fX = 4.19 MHz operation) 51 PD75336 AC CHARACTERISTICS (Ta = -40 to +85 C, VDD = 2.7 to 6.0 V) PARAMETER CPU clock cycle time (minimum instruction execution time = 1 machine cycle)*1 TI0, TI1 input frequency SYMBOL TEST CONDITIONS Operating on main system clock tCY Operating on subsystem clock fTI VDD = 4.5 to 6.0 V VDD = 4.5 to 6.0 V MIN. 0.95 3.8 114 0 0 TI0, TI1 input width high/low tTIH, tTIL INT0 Interrupt input width high/low tINTH, tINTL INT1, INT2, INT4 KR0 to KR7 RESET width low tRSL 10 10 10 VDD = 4.5 to 6.0 V 0.48 1.8 *2 122 TYP. MAX. 64 64 125 1 275 UNIT s s s MHz kHz s s s s s s * 1. CPU clock () cycle time is determined by the oscillator frequency of the connected resonator, the system clock control register (SCC) and the processor clock control register (PCC). The figure at the right indicates the cycle time tCY versus supply voltage VDD characteristic with the main system clock operating. 2. 2tCY or 128/fX is set by setting the interrupt mode register (IM0). Cycle Time tCY [ s] tCY vs VDD (Operating on Main System Clock) 70 64 60 6 5 4 3 Guaranteed Operating Range 2 1 0.5 0 1 2 3 4 5 6 Supply Voltage VDD [V] 52 PD75336 SERIAL TRANSFER OPERATION 2-Wired and 3-Wired Serial I/O Modes (SCK ... Internal clock output) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY1 3800 tKL1 SCK width high/low tKH1 SI setup time (to SCK) SI hold time (from SCK) SO output delay time from SCK tSIK1 tKCY1/2-150 150 ns ns VDD = 4.5 to 6.0 V tKCY1/2-50 ns ns MIN. 1600 TYP. MAX. UNIT ns tKSI1 VDD = 4.5 to 6.0 V 400 250 1000 ns ns ns tKSO1 RL = 1 k, CL = 100 pF* 2-Wired and 3-Wired Serial I/O Modes (SCK ... External clock input) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY2 3200 tKL2 SCK width high/low tKH2 tSIK2 VDD = 4.5 to 6.0 V 400 1600 100 ns ns ns ns MIN. 800 TYP. MAX. UNIT ns SI setup time (to SCK) SI hold time (from SCK ) SO output delay time from SCK tKSI2 VDD = 4.5 to 6.0 V 400 300 1000 ns ns ns tKSO2 RL = 1 k, CL = 100 pF* * RL and CL are load resistor and load capacitance of the SO output line. 53 PD75336 SBI Mode (SCK ... Internal clock output (Master)) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY3 3800 tKL3 SCK width high/low tKH3 SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 width low SB0, 1 width high tSIK3 tKCY3/2-150 150 ns ns VDD = 4.5 to 6.0 V tKCY3/2-50 ns ns MIN. 1600 TYP. MAX. UNIT ns tKSI3 VDD = 4.5 to 6.0 V tKCY3/2 0 0 tKCY3 tKCY3 tKCY3 tKCY3 250 1000 ns ns ns ns ns ns ns tKSO3 RL = 1 k, CL = 100 pF* tKSB tSBK tSBL tSBH SBI Mode (SCK ... External clock input (Slave)) PARAMETER SYMBOL TEST CONDITIONS VDD = 4.5 to 6.0 V SCK cycle time tKCY4 3200 tKL4 SCK width high/low tKH4 SB0, 1 setup time (to SCK ) SB0, 1 hold time (from SCK ) SB0, 1 output delay time from SCK SB0, 1 from SCK SCK from SB0, 1 SB0, 1 width low SB0, 1 width high tSIK4 1600 100 ns ns VDD = 4.5 to 6.0 V 400 ns ns MIN. 800 TYP. MAX. UNIT ns tKSI4 VDD = 4.5 to 6.0 V tKCY4/2 0 0 tKCY4 tKCY4 tKCY4 tKCY4 300 1000 ns ns ns ns ns ns ns tKSO4 RL = 1 k, CL = 100 pF* tKSB tSBK tSBL tSBH * RL and CL are load resistor and load capacitance of the SB0, 1 output lines. 54 PD75336 AC Timing Test Point (Excluding X1 and XT1 inputs) 0.8 VDD 0.2 VDD Test Points 0.8 VDD 0.2 VDD Clock Timings 1/fX tXL tXH X1 Input VDD -0.5 V 0.4 V 1/fXT tXTL tXTH XT1 Input VDD -0.5 V 0.4 V TI0 Timing 1/fTI tTIL tTIH TI0 55 PD75336 Serial Transfer Timing 3-wired serial I/O mode: tKCY1 tKL1 tKH1 SCK tSIK1 tKSI1 SI tKSO1 Input Data SO Output Data 2-wired serial I/O mode: tKCY2 tKL2 tKH2 SCK tSIK2 tKSI2 SB0,1 tKSO2 56 PD75336 Serial Transfer Timing Bus release signal transfer: tKL3,4 tKCY3,4 tKH3,4 SCK tSIK3,4 tKSB tSBL tSBH tSBK tKSI3,4 SB0,1 tKSO3,4 Command signal transfer: tKCY3,4 tKH3,4 tKL3,4 SCK tSIK3,4 tKSB tSBK tKSI3,4 SB0,1 tKSO3,4 Interrupt Input Timing tINTL tINTH INT0,1,2,4 KR0-7 RESET Input Timing tRSL RESET 57 PD75336 DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = -40 to 85 C) PARAMETER Data retention supply voltage Data retention supply current*1 Release signal setup time Oscillation stabilization wait time*2 SYMBOL VDDDR IDDDR tSREL Release by RESET tWAIT Release by interrupt request *3 ms VDDDR = 2.0 V 0 217/fx TEST CONDITIONS MIN. 2.0 0.1 TYP. MAX. 6.0 10 UNIT V A s ms * 1. Current which flows in the on-chip pull-up resistor is not included. 2. The oscillation stabilization wait time is the time during which the CPU operation is stopped to prevent unstable operation at the oscillation start. 3. Depends on the basic interval timer mode register (BTM) setting (table below). BTM3 -- -- -- -- BTM2 0 0 1 1 BTM1 0 1 0 1 BTM0 0 1 1 1 WAIT TIME (Figures in parentheses are for operation at fx = 4.19 MHz) 220/fx (approx. 250 ms) 217/fx (approx. 31.3 ms) 215/fx (approx. 7.82 ms) 213/fx (approx. 1.95 ms) 58 PD75336 Data Retention Timing (STOP mode release by RESET) Internal Reset Operation HALT Mode STOP Mode Data Retention Mode Operating Mode VDD VDDDR STOP Instruction Execution tSREL RESET tWAIT Data Retention Timing (Standby release signal: STOP mode release by interrupt signal) HALT Mode STOP Mode Data Retention Mode Operating Mode VDD VDDDR STOP Instruction Execution tSREL Standby Release Signal (Interrupt Request) tWAIT 59 PD75336 11. PACKAGE INFORMATION 80 PIN PLASTIC QFP ( 14) A B 60 61 41 40 detail of lead end D C S 80 1 21 20 F G H IM J K P N L S80GC-65-3B9-3 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 17.2 0.4 14.0 0.2 14.0 0.2 17.2 0.4 0.8 0.8 0.30 0.10 0.13 0.65 (T.P.) 1.6 0.2 0.8 0.2 0.15+0.10 -0.05 0.10 2.7 0.1 0.1 3.0 MAX. M INCHES 0.677 0.016 0.551+0.009 -0.008 0.551+0.009 -0.008 0.677 0.016 0.031 0.031 0.012+0.004 -0.005 0.005 0.026 (T.P.) 0.063 0.008 0.031+0.009 -0.008 0.006+0.004 -0.003 0.004 0.106 0.004 0.004 0.119 MAX. 60 55 Q PD75336 80 PIN PLASTIC TQFP (FINE PITCH) ( 12) A B 60 61 41 40 detail of lead end D C S 80 21 1 20 F G H IM J K P N L P80GK-50-BE9-3 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 14.0 0.4 12.0 0.2 12.0 0.2 14.0 0.4 1.25 1.25 0.20 0.10 0.10 0.5 (T.P.) 1.0 0.2 0.5 0.2 0.125 +0.10 -0.05 0.10 1.05 0.05 0.05 1.27 MAX. M INCHES 0.551 0.016 0.472+0.009 -0.008 0.472+0.009 -0.008 0.551 0.016 0.049 0.049 0.008 0.004 0.004 0.020 (T.P.) 0.039 -0.008 0.020+0.008 -0.009 0.005+0.004 -0.001 0.004 0.041 0.002 0.002 0.05 MAX. +0.009 55 Q 61 PD75336 5 12. RECOMMENDED SOLDERING CONDITIONS The PD75336 should be soldered and mounted under the conditions recommended in the table below. For detail of recommended soldering conditions, refer to information document "Surface Mount Technology Manual" (IEI-1207). For soldering methods and conditions other than those recommended below, contact our salesman. Table 12-1 Surface Mounting Type Soldering Conditions (1) PD75336GC-xxx-3B9 : 80-pin plastic QFP ( 14mm) Soldering Conditions Package peak temperature: 230C, Duration: 30 sec. max. (at 210C above), Number of times: Once, Time limit: 7 days* (thereafter 10 hours prebaking required at 125C) Package peak temperature: 215C, Duration: 40 sec. max. (at 200C above), Number of times: Once, Time limit: 7 days* (thereafter 10 hours prebaking required at 125C) Solder bath temperature: 260C max., Duration: 10 sec. max., Number of times: Once, Preliminary heat temperature: 120C max. (Package surface temperature), Time limit: 7 days* (thereafter 10 hours prebaking required at 125C) Pin part temperature: 300C max., Duration: 3 sec. max. (per device side) Recommended Condition Symbol Soldering Method Infrared reflow IR30-107-1 VPS VP15-107-1 Wave soldering WS60-107-1 Pin part heating (2) PD75336GK-xxx-BE9 : 80-pin plastic TQFP (fine pitch)( 12mm) Soldering Conditions Package peak temperature: 230C, Duration: 30 sec. max. (at 210C above), Number of times: Once, Time limit: 1 days* (thereafter 16 hours prebaking required at 125C) Package peak temperature: 215C, Duration: 40 sec. max. (at 200C above), Number of times: Once, Time limit: 1 days* (thereafter 16 hours prebaking required at 125C) Pin part temperature: 300C max., Duration: 3 sec. max. (per device side) Recommended Condition Symbol Soldering Method Infrared reflow IR30-161-1 VPS VP15-161-1 Pin part heating * For the storage period after dry-pack decompression, storage conditions are max. 25C, 65% RH. Use of more than one soldering method should be avoided (except in the case of pin part heating). Note Notice A version of this product with improved recommended soldering conditions is available. For details (improvements such as infrared reflow peak temperature extension (235C), number of times: twice, relaxation of time limit, etc.), contact NEC sales personnel. 62 PD75336 APPENDIX A. DIFFERENCES BETWEEN PD75336 AND PD75328 FUNCTIONS Product Name CPU core ROM (Byte) RAM (x 4 bits) General register Main system clock Instruction cycle Subsystem clock PD75336 75X High End 16256 768 4 bits x 8 x 4 0.95 s, 1.91 s, 3.81 s, 15. 3 s (at 4.19 MHz operation) PD75328 75X Standard 8064 512 4 bits x 8 x 1 0.95 s, 1.91 s, 15.3 s (at 4.19 MHz operation) 122 s (at 32.768 kHz operation) * 8-bit resolution x 8 channels (successive approximation) * A/D operating range: VDD = 2.7 to 6.0 V * Basic interval timer x 1 * Timer/event counter x 2 * Watch timer x 1 * External: 3 * Internal: 4 2 kHz, 4 kHz, 32 kHz Transfer, add/subtract, increase/decrease, compare * 80-pin plastic QFP ( 14 mm) * 80-pin plastic TQFP (fine pitch)( A/D converter * 8-bit resolution x 6 channels (successive approximation) * A/D operating range: VDD = 3.5 to 6.0 V * Basic interval timer x 1 * Timer/event counter x 1 * Watch timer x 1 * External: 3 * Internal: 3 2 kHz Transfer * 80-pin plastic QFP ( 14 mm) Timer/counter Vectored interrupt Buzzer output (BUZ) 8-bit data processing Package Product with on-chip PROM 12 mm) PD75P336 PD75P328 63 PD75336 APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for system development using the PD75336. IE-75000-R*1 IE-75001-R IE-75000-R-EM*2 EP-75336GC-R Hardware EV-9200GC-80 EP-75336GK-R EV-9500GK-80 PG-1500 PA-75P328GC PA-75P336GK Software IE control program PG-1500 controller RA75X relocatable assembler 75X series in-circuit emulator IE-75000-R/IE-75001-R emulation board PD75336 emulation probe. 80-pin conversion socket EV-9200GC-80 added. PD75336 emulation probe. 80-pin conversion socket EV-9500GK-80 added. PROM programmer PD75P336GC PROM programmer adapter, connected to PG-1500 PD75P336GK PROM programmer adapter, connected to PG-1500 Host Machine * PC-9800 series (MS-DOSTM Ver. 3.30 to 5.00A*3 ) * IBM PC/ATTM (PC DOSTM Ver. 3.1) * 1. Maintenance products 2. Not incorporated in the IE-75001-R. 3. The task swap function, which is provided with Ver. 5.00/5.00A, is not available with this software. 5 Remarks For development tools manufactured by a third party, see the "75X Series Selection Guide (IF-151)". 64 PD75336 APPENDIX C. RELATED DOCUMENTS 5 Device Related Documents Document Name User's Manual Instruction Application Table 75X Series Selection Guide Document Number Development Tools Related Documents Document Name IE-75000-R/IE-75001-R User's Manual Hardware IE-75000-R-EM User's Manual EP-75336GC-R User's Manual EP-75336GK-R User's Manual PG-1500 User's Manual Software Operation Volume RA75X Assembler Package User's Manual Language Volume PG-1500 Controller User's Manual Document Number Other Related Documents Document Name Package Manual Surface Mount Technology Manual Quality Grade on NEC Semiconductor Devices NEC Semiconductor Device Reliability & Quality Control Electrostatic Discharge (ESD) Test Semiconductor Devices Quality Guarantee Guide Microcomputer Related Products Guide Other Manufactures Volume Document Number Note The contents of the above related documents are subject to change without notice. The latest documents should be used for design, etc. 65 PD75336 66 PD75336 67 PD75336 [MEMO] No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. M4 92.6 MS-DOS is a trademark of Microsoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation. |
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